Andrew Lukefahr

Assistant Professor
Intelligent Systems Engineering
Indiana University

lukefahr@iu.edu

2032 Luddy Hall
700 N. Woodlawn Ave
Bloomington, IN 47405

Home

Research

Publications

Teaching

Conference Papers

ReCon: From the Bitstream to Piracy Detection

By Grant Skipper, Christopher Sozio, Adam Duncan, Andrew Lukefahr, and Martin Swany.
In 2020 IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). 2020.
[Paper]

SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment

By A. Duncan, A. Nahiyan, F. Rahman, G. Skipper, M. Swany, Andrew Lukefahr, F. Farahmandi, and M. Tehranipoor.
In 2020 IEEE 38th VLSI Test Symposium (VTS), volume, 1–6. 2020.
[Paper]

FPGA Bitstream Security: A Day in the Life

By A. Duncan, F. Rahman, Andrew Lukefahr, F. Farahmandi, and M. Tehranipoor.
In 2019 IEEE International Test Conference (ITC), volume, 1–10. 2019.
[Paper | Slides]

FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection

By Adam Duncan, Grant Skipper, Andrew Stern, Adib Nahiyan, Fahim Rahman, Andrew Lukefahr, Mark Tehranipoor, and Martin Swany.
In 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 81–90. IEEE, 2019.
[Paper | Slides]

Mirage cores: The illusion of many out-of-order cores using in-order hardware

By Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke.
In Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 745–758. 2017.
[Paper | Slides]

Scalpel: Customizing DNN pruning to the underlying hardware parallelism

By J. Yu, A. Lukefahr, D. Palframan, G. Dasika, R. Das, and S. Mahlke.
In 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), volume. 2017.
[Paper | Slides]

Dynamos: dynamic schedule migration for heterogeneous cores

By Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke.
In Proceedings of the 48th International Symposium on Microarchitecture (MICRO), 322–333. 2015.
[Paper | Slides]

Heterogeneous microarchitectures trump voltage scaling for low-power cores

By Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald Dreslinski Jr, Thomas F Wenisch, and Scott Mahlke.
In Proceedings of the 23rd international conference on Parallel architectures and compilation (PACT), 237–250. 2014.
[Paper | Slides]

Trace based phase prediction for tightly-coupled heterogeneous cores

By Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke.
In 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 445–456. IEEE, 2013.
[Paper | Slides]

Composite cores: Pushing heterogeneity into a core

By Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M Sleiman, Ronald Dreslinski, Thomas F Wenisch, and Scott Mahlke.
In 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 317–328. IEEE, 2012.
[Paper | Slides]

Towards Semantics-directed System Design and Synthesis

By William L Harrison, Benjamin Schulz, Adam Procter, Andrew Lukefahr, and Gerard Allwein.
In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 1. 2011.

Journal Papers

TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers

By Jiecao Yu, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke.
In ACM Transactions on Embedded Computing Systems (TECS) 18(5s):1–21 2019
[Paper | Slides]

Exploring fine-grained heterogeneity with composite cores

By Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M Sleiman, Ronald G Dreslinski, Thomas F Wenisch, and Scott Mahlke.
In IEEE Transactions on Computers 65(2):535–547 2015
[Paper]

Patents

Field-Programmable Gate Array with Updatable Security Schemes

By Adam Duncan and Andrew Lukefahr.
US Patent Application: 17/104,648. 2020.

Heterogeneity within a processor core

By Andrew Lukefahr, Reetuparna Das, Shruti Padmanabha, and Scott Mahlke.
US Patent 9,639,363. May 2017.

Control of switching between executed mechanisms

By Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke.
US Patent 9,870,226. January 2018.

Recording performance metrics to predict future execution of large instruction sequences on either high or low performance execution circuitry

By Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke.
US Patent 9,965,279. May 2018.

Controlling transition between using first and second processing circuitry

By Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Scott Mahlke, and Jiecao Yu.
US Patent 10,310,858. June 2019.

Method of detecting repetition of an out-of-order execution schedule, apparatus and computer-readable medium

By Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke.
US Patent 10,613,866. April 2020.

Systems and devices for compressing neural network parameters

By Jiecao Yu, Andrew Lukefahr, David Palframan, Ganesh Dasika, Reetuparna Das, and Scott Mahlke.
US Patent Application 15/629,560. June 2017.

Systems and devices for formatting neural network parameters

By Jiecao Yu, Andrew Lukefahr, David Palframan, Ganesh Dasika, Reetuparna Das, and Scott Mahlke.
US Patent Application 15/629,394. June 2017.

Workshops

Adaptive Cache Partitioning on a Composite Core

By Jiecao Yu, Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, and Scott Mahlke.
In The PRISM-3 Workshop at The International Symposium on Computer Architecture (ISCA-45). June 2015.

Performance Prediction Models

By Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke.
In Gem5 Users Workshop at The International Symposium on Microarchitecture (MICRO-45). December 2012.